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general description the MAX6853 compact vacuum-fluorescent display (vfd) controller provides microprocessors with the mul- tiplex timing for 5 x 7 matrix vfd displays up to 96 characters and controls industry-standard, shift-regis- ter, high-voltage grid/anode vfd tube drivers. the device supports display tubes using either one or two digits per grid, as well as universal displays. the MAX6853 provides an internal crosspoint switch to match any tube-driver shift-register grid/anode order, and is compatible with both chip-in-glass and external tube drivers. hardware is included to simplify the gen- eration of cathode bias and filament supplies and to pro- vide up to five logic outputs, including a buzzer driver. the MAX6853 includes an ascii 104-character font, multiplex scan circuitry, and static ram that stores digit, cursor, and annunciator data, as well as font data for 24 user-definable characters. an internal 16-step digital brightness control adjusts the display intensity. the device also includes separate annunciator and cur- sor control with automatic blinking, as well as a low- power shutdown mode. the MAX6853 provides timing to generate the pwm waveforms to drive the tube filament from a dc supply. the filament drive is synchronized to the display multi- plexing to eliminate beat artifacts. for an spi-compatible version, refer to the max6852 data sheet. applications features 400kbps 2-wire i 2 c-compatible interface 2.7v to 3.6v operation controls up to 96 5 x 7 matrix characters one digit and two digits per grid and universal displays supported 16-step digital brightness control built-in ascii 104-character font 24 user-definable characters up to four annunciators per grid with automatic blinking control separate cursor control with automatic blinking filament drive full-bridge waveform synthesis buzzer tone generator with single-ended or push-pull driver up to five general-purpose logic outputs 9a low-power shutdown (data retained) 16-pin qsop package MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller ________________________________________________________________ maxim integrated products 1 ordering information 19-2673; rev 0; 10/02 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. part temp range pin-package MAX6853aee -40 c to +125 c 16 qsop display modules retail pos displays weight and tare displays bar graph displays industrial controllers spi is a trademark of motorola, inc. MAX6853 vfclk vfdout vfload vfblank osc2 sda v+ scl ad0 osc1 sda scl microcontroller 56pf 0.1 f gnd chip-on-glass vfd vfd supply voltage 10k ? typical application circuit pin configuration and functional diagram appear at end of data sheet.
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage (with respect to gnd) v+ .............................................................................-0.3v to +4v ad0, sda, scl......................................................-0.3v to +5.5v all other pins................................................-0.3v to (v+ + 0.3v) current v+..................................................................................200ma gnd .............................................................................-200ma phase1, phase2, port0, port1, pump................150ma vfclk, vfdout, vfload, vfblank ......................150ma sda .................................................................................15ma continuous power dissipation (t a = +70 c) 16-pin qsop (derate at 8.34mw/ c above +70 c).....667mw operating temperature range (t min , t max ) MAX6853aee................................................-40 c to +125 c junction temperature ......................................................+150 c storage temperature range .............................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c dc electrical characteristics (typical operating circuit, v+ = 2.7v to 3.6v, t a = t min to t max , unless otherwise noted.) (note 1) parameter symbol conditions min typ max units operating supply voltage v+ 2.7 3.6 v t a = t min to t max 160 shutdown supply current i shdn shutdown mode, all digital inputs at v+ or gnd t a = +25 c920 a t a = t min to t max 3 operating supply current i+ osc = 4mhz vfload, vfdout, vfclk, vfblank, loaded 100pf t a = +25 c 1.65 2 ma master clock frequency (osc internal oscillator) f osc osc1 fitted with c osc = 56pf, osc2 fitted with r osc = 10k ? ; see the typical operating circuit 4 mhz master clock frequency (osc external oscillator) osc1 overdriven with external f osc 2 8 mhz dead-clock protection frequency 200 khz osc high time t ch 50 ns osc low time t cl 50 ns fast or slow segment blink duty cycle (note 2) 49.5 50.5 % logic inputs and outputs input leakage current ad0, sda, scl i ih , i il 0.2 1 a logic-high input voltage ad0, sda, scl v ih 2.4 v logic-low input voltage ad0, sda, scl v il 0.6 v sda output low voltage v olsda i sink = 3ma 0.5 v input capacitance c i 10 pf
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units output rise and fall time phase1, phase2, port0, port1, pump, vfload, vfdout, vfclk, vfblank t rft c load = 100pf 25 ns output high-voltage phase1, phase2, port0, port1, pump, vfload, vfdout, vfclk, vfblank v oh i source = 10ma v + - 0.6 v output low-voltage phase1, phase2, port0, port1, pump, vfload, vfdout, vfclk, vfblank v ol i sink = 10ma 0.4v v output short-circuit source current phase1, phase2, port0, port1, pump, vfload, vfdout, vfclk, vfblank i ohsc output programmed high, output short circuit to gnd (note 2) 62 125 ma output short-circuit sink current phase1, phase2, port0, port1, pump, vfload, vfdout, vfclk, vfblank i olsc output programmed low, output short circuit to v+ (note 2) 72 125 ma i 2 c timing characteristics (figure 6) serial clock frequency f scl 400 khz bus free time between a stop and a start condition t buf 1.3 s hold time (repeated) start condition t hd , sta 0.6 s repeated start condition setup time t su , sta 0.6 s stop condition setup time t su , sto 0.6 s data hold time t hd , dat (note 3) 0.9 s data setup time t su , dat 100 ns scl clock low period t low 1.3 s scl clock high period t high 0.6 s rise time of both sda and scl signals, receiving t r (notes 2, 4) 20 + 0.1c b 300 ns fall time of both sda and scl signals, receiving t f (notes 2, 4) 20 + 0.1c b 300 ns dc electrical characteristics (continued) (typical operating circuit, v+ = 2.7v to 3.6v, t a = t min to t max , unless otherwise noted.) (note 1)
typical operating characteristics (typical operating circuit, v+ = 3.3v, t a = +25 c, unless otherwise noted.) supply current vs. supply voltage MAX6853 toc01 v cc (v) i cc (ma) 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 1.3 1.5 1.7 1.9 2.1 1.1 2.7 3.6 t a = +125 c t a = +25 c t a = -40 c shutdown supply current vs. supply voltage (osc = 1) MAX6853 toc02 v+ (v) i supply ( a) 3.5 3.3 3.1 2.9 5 15 20 35 40 45 50 0 2.7 t a = -40 c osc1 = 0 t a = +25 c t a = +125 c 10 25 30 frequency (mhz) 7 6 5 4 3 200 400 600 800 1000 1200 1400 0 28 shutdown supply current vs. external osc frequency MAX6853 toc03 i supply ( a) MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units fall time of sda transmitting t f (notes 2, 5) 20 + 0.1c b 250 ns pulse width of spike suppressed t sp (note 6) 0 50 ns capacitive load for each bus line cb (note 2) 400 pf vfd interface timing characteristics (figure 14) vfclk clock period t vcp (note 2) 250 1050 ns vfclk pulse width high t vch (note 2) 125 ns vfclk pulse width low t vcl (note 2) 125 ns vfclk rise to vfd load rise hold time t vcsh (note 2) 19 s vfdout setup time t vds (note 2) 50 ns vfload pulse high t vcsw (note 2) 245 ns dc electrical characteristics (continued) (typical operating circuit, v+ = 2.7v to 3.6v, t a = t min to t max , unless otherwise noted.) (note 1) note 1: all parameters tested at t a = +25 c. specifications over temperature are guaranteed by design. note 2: guaranteed by design. note 3: a master device must provide a hold time of at least 300ns for the sda signal (referred to v il of the scl signal) in order to bridge the undefined region of scl s falling edge. note 4: c b = total capacitance of one bus line in pf. t r and t f measured between 0.3v+ and 0.7v+. note 5: i sink 6ma. c b = total capacitance of one bus line in pf. t r and t f measured between 0.3v+ and 0.7v+. note 6: input filters on the sda and scl inputs suppress noise spikes less than 50ns.
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller _______________________________________________________________________________________ 5 80 60 40 20 0 100 output low voltage vs. i sink MAX6853 toc04 i sink (ma) v ol (v) 0.2 0.6 0.8 1.4 1.6 1.8 2.0 0 t a = -40 c 0.4 1.0 1.2 v+ = 3.3v v+ = 3.6v v+ = 2.7v 80 60 40 20 0 100 output low voltage vs. i sink MAX6853 toc05 i sink (ma) v ol (v) 0.2 0.6 0.8 1.4 1.6 1.8 2.0 0 t a = +25 c 0.4 1.0 1.2 v+ = 3.6v v+ = 2.7v v+ = 3.3v 80 60 40 20 0 100 output low voltage vs. i sink MAX6853 toc06 i sink (ma) v ol (v) 0.2 0.6 0.8 1.4 1.6 1.8 2.0 0 t a = +125 c 0.4 1.0 1.2 v+ = 3.6v v+ = 2.7v v+ = 3.3v 80 60 40 20 0 100 v in - v oh vs. i source MAX6853 toc07 i source (ma) v ol (v) 0.5 1.5 2.0 0 1.0 t a = -40 c v+ = 3.6v v+ = 2.7v v+ = 3.3v 80 60 40 20 0 100 v in - v oh vs. i source MAX6853 toc08 i source (ma) v ol (v) 0.2 0.6 0.8 1.4 1.6 1.8 2.0 0 t a = +25 c 0.4 1.0 1.2 v+ = 3.6v v+ = 2.7v v+ = 3.3v 80 60 40 20 0 100 v in - v oh vs. i source MAX6853 toc09 i source (ma) v ol (v) 0.5 1.5 2.0 0 1.0 t a = +125 c v+ = 3.6v v+ = 2.7v v+ = 3.3v typical operating characteristics (continued) (typical operating circuit, v+ = 3.3v, t a = +25 c, unless otherwise noted.) f osc vs. temperature MAX6853 toc10 temperature ( c) f osc (mhz) 110 95 80 65 50 35 20 5 -10 -25 0.5 1.0 1.5 2.0 2.5 0 -40 125 v+ = 2.7v v+ = 3.3v v+ = 3.6v dead-clock osc frequency vs. temperature MAX6853 toc11 temperature ( c) frequency (mhz) 110 95 80 65 50 35 20 5 -10 -25 -40 125 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0 v+ = 2.7v v+ = 3.6v v+ = 3.3v
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller 6 _______________________________________________________________________________________ 6 _______________________________________________________________________________________ grid 1 grid 2 grid 3 grid 4 grid 5 grid 6 grid 7 grid 8 grid 10 grid 9 grid 11 grid 12 grid 13 grid 14 grid 15 grid 16 figure 1. example of a one-digit-per-grid display pin description pin name function 1 vfclk serial-clock output to external driver. push-pull clock output to external display driver. on vfclk s falling edge, data is clocked out of vfdout. 2 vfdout serial-data output to external driver. push-pull data output to external display driver. 3 vfload serial-load output to external driver. push-pull load output to external display driver. rising edge is used by external display driver to load serial data into display latch. 4 vfblank display blanking output to external driver. push-pull blanking output to external display driver used for pwm intensity control. 5 pump pump general-purpose output. user-configurable push-pull logic output. 6 phase1 filament drive phase1 output and general-purpose output. user-configurable push-pull logic output can also be used as a driver for external filament bridge drive. 7 phase2 filament drive phase2 output and general-purpose output. user-configurable push-pull logic output can also be used as a driver for external filament bridge drive. 8 v+ positive supply voltage. bypass v+ to gnd with a 0.1f ceramic capacitor. 9 gnd ground 10 port0 port0 general-purpose output. user-configurable push-pull logic output. 11 scl serial-clock input 12 sda serial-data i/o 13 ad0 address input 0. sets device slave address. connect to either gnd, v+, scl, or sda to give four logic combinations. see table 7. 14 port1 port1 general-purpose output. user-configurable push-pull logic output. 15 osc2 multiplex clock input 2. connect resistor r osc from osc2 to gnd. 16 osc1 multiplex clock input 1. to use the internal oscillator, connect capacitor c osc from osc1 to gnd. to use the external clock, drive osc1 with a 2mhz to 8mhz cmos clock.
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller _______________________________________________________________________________________ 7 detailed description overview of the MAX6853 the MAX6853 vfd controller generates the multiplex timing for the following vfd display types: multiplexed displays with one digit per grid, and up to 48 grids (in 48/1 mode). each grid can contain one 5 x 7 matrix character, a dp segment, a cursor segment, and four extra annunciator segments (figure 1). multiplexed displays with two digits per grid, and up to 48 grids (in 96/2 mode). each grid can contain two 5 x 7 matrix characters, two dp segments, and two cursor segments. no annunciator segments are supported (figure 2). each digit can have a 5 x 7 matrix character, a dp seg- ment, a cursor segment, and (for one-digit-per-grid dis- plays only) four annunciators (figure 3). the 5 x 7 matrix character segments are not controlled directly, but use on-chip fonts that map the segments. the fonts comprise an ascii 104-character fixed-font set, and 24 user-definable characters. the predefined characters follow the arial font, with the addition of the following common symbols: , , , , , , , and . the 24 user-definable characters are uploaded by the user into on-chip ram through the serial interface and are lost when the device is powered down. as well as custom 5 x 7 characters, the user-definable fonts can control up to 35 custom segments, bar graphs, or graphics. annunciator segments have individual, independent control, so any combination of annunciators can be lit. annunciators can be off, lit, or blink either in phase or out of phase with the cursor. the blink-speed control is software selectable to be one or two blinks per second (osc = 4mhz). dp segments can be lit or off, but have no blink control. a dp segment is set by the same command that writes the digit s 5 x 7 matrix character. the cursor segment is controlled differently. a single register selects one digit s cursor from the entire dis- play, and that can be lit either continuously or blinking. all the other digits cursors are off. the designations of dp, cursor, and annunciator are interchangeable. for example, consider an application requiring only one dp lit at a time, but the dp needs to grid 1 grid 2 grid 3 grid 4 grid 5 grid 6 grid 7 grid 8 figure 2. example of a two-digits-per-grid display (8 grids, 16 digits) c fph mw 4 annunciator segments decimal point (dp) segment cursor segment 5 x 7 matrix character with 35 segments figure 3. digit structure with 5 ? 7 matrix character, dp segment, cursor segment, four annunciators
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller 8 _______________________________________________________________________________________ blink. the dp function does not have blink capability. instead, the dp segments on the display are routed (using the output map) to the cursor function. in this case, the dp segments are controlled using the cursor register. the output of the controller is a 4-wire serial stream that interfaces to industry-standard, shift-register, high-volt- age grid/anode vfd tube drivers (figure 4). this inter- face uses three outputs to transfer and latch grid and anode data into the tube drivers, and a fourth output that enables/disables the tube driver outputs (figure 5). the enable/disable control is modulated by the MAX6853 for both pwm intensity control and interdigit blanking, and disables the tube driver in shutdown. the controller multiplexes the display by enabling each grid of the vfd in turn for 100s (osc = 4mhz) with the cor- rect segment (anode) data. the data for the next grid is transferred to the tube drivers during the display time of the current grid. the controller uses an internal output map to match any tube-driver s shift-register grid/anode order, and is therefore compatible with all vfd internal chip-in-glass or external tube drivers. the MAX6853 provides five high-current output ports, which can be configured for a variety of functions: the pump output can be configured as either an 80khz (osc = 4mhz) clock intended for dc-to-dc converter use or a general-purpose logic output. the phase1 and phase2 outputs can be individually configured as either 10khz pwm outputs (osc = 4mhz) intended for filament driving, blink status out- puts, or general-purpose logic outputs. the port0 and port1 outputs can be individually con- figured as either 625hz, 1250hz, or 2500hz clocks (osc = 4mhz) intended for buzzer driving, blink or shutdown status outputs, or general-purpose logic outputs. display modes the MAX6853 has two display modes (table 1), select- ed by the m bit in the configuration register (table 23). the display modes trade the maximum allowable num- MAX6853 vfclk vfdout vfload vfblank port0 sda v+ 3.3v scl ad0 port1 sda scl microcontroller gnd vfd tube driver piezo sounder grid/anode drivers vfd tube ac filament supply from mains transformer zener diode bias 115v 5v figure 4. connection of the MAX6853 to vfd driver and vfd tube serial-to-parallel shift register latches vfclk vfdin vfload vfblank o0 o0 o1 o1 o2 o2 on-2 on-2 on-1 on-1 on on vfd tube driver vfd tube simplified figure 5. block diagram of vfd tube driver and vfd tube
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller _______________________________________________________________________________________ 9 ber of digits (96/2 mode) against the availability of annunciator segments (48/1 mode). table 2 is the reg- ister address map. initial power-up initial power-up resets all control registers, clears dis- play segment and annunciator data, sets intensity to minimum, and enables shutdown. (table 3). character registers the MAX6853 uses 48 character registers (48/1 mode) (table 4) or 96 character registers (96/2 mode) (table 5) to store the 5 x 7 characters (table 6). each digit is represented by 1 byte of memory. the data in the char- acter registers does not control the character segments directly. instead, the register data is used to address a character generator, which stores the data of the 128- character font (table 9). the lower 7 bits of the charac- ter data (d6 to d0) select a character from the font table. the most significant bit (msb) of the register data (d7) controls the dp segment of the digit; it is set to light the dp, cleared to leave it unlit. the character registers address maps are shown in table 4 (48/1 mode) and table 5 (96/2 mode). in 48/1 mode, the character registers use a single address range 0x20 to {0x20 + g}, where g is the value in the grids register (table 25). the 48/1 mode upper address limit, when g is 0x2f, is therefore 0x4f. the address range 0x50 to 0x7f is used for annunciator data in 48/1 mode. in 96/2 mode, the character registers use two address ranges. the first row s address range is 0x20 to {0x20 + g}. the second row s address range is 0x50 to {0x50 + g}. therefore, in 96/2 mode, the character regis- ters are only one contiguous memory range when a 48- grid display is used. display mode maximum no. of digits maximum no. of annunciators maximum no. of grids digits covered by each grid 48/1 mode 48 digits, each with a dp segment and a cursor segment 4 per digit 1 digit per grid 96/2 mode 96 digits, each with a dp segment and a cursor segment none 48 grids 2 digits per grid table 1. display modes command address register d15 d14 d13 d12 d11 d10 d9 d8 hex code no-op r/ w 0000000 0x00 vfblank polarity r/ w 0000001 0x01 intensity r/ w 0000010 0x02 grids r/ w 0000011 0x03 configuration r/ w 0000100 0x04 user-defined fonts r/ w 0000101 0x05 output map r/ w 0000110 0x06 display test and device id r/ w 0000111 0x07 pump register r/ w 0001000 0x08 filament duty cycle r/ w 0001001 0x09 phase1 r/ w 0001010 0x0a phase2 r/ w 0001011 0x0b port0 r/ w 0001100 0x0c port1 r/ w 0001101 0x0d shift limit r/ w 0001110 0x0e cursor r/ w 0001111 0x0f factory reserved. do not write to register. x 0010000 0x10 table 2. register address map
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller 10 ______________________________________________________________________________________ character generator font mapping the font is a 5 x 7 matrix comprising 104 characters in rom, and 24 user-definable characters. the selection from the total of 128 characters is represented by the lower 7 bits of the 8-bit digit registers. the msb, shown as x in the rom map (table 9), controls the dp seg- ment of the digit; it is set to light the dp, cleared to leave it unlit. the character map follows the arial font for 96 charac- ters in the x0100000 through x1111111 range. the first 32 characters map the 24 user-definable positions (ram00 to ram23), plus eight extra common charac- ters in rom. user-defined fonts the 24 user-definable characters are represented by 120 entries of 7-bit data, five entries per character, and are stored in the MAX6853 s internal ram. the 120 user-definable font data entries are written and read through a single register, address 0x05. an autoincrementing font address pointer in the MAX6853 indirectly accesses the font data. the font address pointer can be written, setting one of 120 addresses between 0x00 and 0xf7, but cannot be read back. the font data is written to and read from the MAX6853 indi- rectly, using this font address pointer. unused font locations can be used as general-purpose scratch ram, noting that the font registers are only 7 bits wide, not 8. register data register power-up condition command address d7 d6 d5 d4 d3 d2 d1 d0 vfblank polarity vfblank is high to disable the display 0x01 x x x x x x 0 0 intensity 1/16 (min on) 0x02 x x x x 0000 grids display has 1 grid 0x03 x x 0 00000 configuration shutdown enabled, configuration unlocked 0x04 1 0 0 0 x 0 0 0 user-defined font address pointer address 0x80; pointing to the first user-defined font location 0x05 1 0 0 00000 user-defined fonts all 24 characters blank 00000000 output map pointer pointing to first entry address 0x06 1 0 0 00000 output map data predefined for 40-digit display see table 30 for power-up patterns. display test normal operation 0x07 0 0 0 00110 pump general-purpose output, logic 0x08 0 0 0 00000 filament duty cycle minimum duty cycle 0x09 0 0 0 00001 phase1 general-purpose output, logic 0x0a 0 0 0 00000 phase2 general-purpose output, logic 0x0b 0 0 0 00000 port0 general-purpose output, logic 0x0c 0 0 0 00000 port1 general-purpose output, logic 0x0d 0 0 0 00001 shift limit 2 output bits 0x0e x 0 0 00001 cursor off 0x0f 0 1 1 00000 character and annunciator data clear 0x20 0 0 0 00000 up to up to character and annunciator data clear 0x7f 0 0 0 00000 table 3. initial power-up register status
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller ______________________________________________________________________________________ 11 table 10 shows how to use the single user-defined font register 0x05 to set the font address pointer, write font data, and read font data. a read action always returns font data from the font address pointer position. a write action sets the 7-bit font address pointer if the msb is set, or writes 7-bit font data to the font address pointer position if the msb is clear. the font address pointer autoincrements after a valid access to the user-definable font data. auto- incrementing allows the 120-font data entries to be writ- ten and read back very quickly because the font point- er address need only be set once. after the last data location 0xf7 has been written, further font data entries are ignored until the font address pointer is reset. if the font address pointer is set to an out-of-range address by writing data in the 0xf8 to 0xff range, then address 0x80 is set instead (table 11). table 12 shows the user-definable font pointer base addresses. table 13 shows an example of data (characters 0, 1, and 2) being stored in the first three user-defined font locations, illustrating the orientation of the data bits. table 14 shows the six sequential write commands required to set a MAX6853 s font character ram02 with the data to display character 2 given in table 9. cursor register the cursor register controls the behavior of the cursor segments (table 15). the MAX6853 controls 48 cursors in 48/1 mode, and 96 cursors in 96/2 mode. the cursor register selects one digit s cursor to be lit either contin- uously or blinking. all the other digits cursors are off. the 7 least significant bits (lsbs) of the cursor register identify the cursor position. the msb is clear for the cursor to be on continuously, and set for the cursor to be lit only during the first half of each blink period. the valid cursor position address range is contiguous: 0 to 47 (0x00 to 0x2f) for the first digit row, and 48 to 95 (0x30 to 0x5f) for the last digit row. if the cursor reg- ister is programmed with an out-of-range value of 95 to 127 (0x60 to 0x7f), then all cursors are off. annunciator registers the annunciator registers are organized in bytes, with each segment of each grid being represented by 2 bits. thus, the four annunciators segments allowed for each grid are represented by exactly 1 byte (table 16). annunciators are only available in 48/1 mode. the annunciator address map is shown in table 4. configuration register the configuration register is used to enter and exit shut- down, lock the key vfd configuration settings, select the blink rate, globally clear the digit and annunciator data, reset the blink timing, and select between 48/1 and 96/2 display modes (table 17). shutdown mode (s data bit d0) format the s bit in the configuration register selects shutdown or normal operation (table 18). the display driver can be programmed while in shutdown mode, and shut- command address register d15 d14 d13 d12 d11 d10 d9 d8 hex code digit 0 5 x 7 matrix character 0 0 1 0 0 0 0 0 0x20 digit 1 5 x 7 matrix character 0 0 1 0 0 0 0 1 0x21 digit 2 5 x 7 matrix character 0 0 1 0 0 0 1 0 0x22 up to digit 45 5 x 7 matrix character 0 1 0 0 1 1 0 1 0x4d digit 46 5 x 7 matrix character 0 1 0 0 1 1 1 0 0x4e digit 47 5 x 7 matrix character 0 1 0 0 1 1 1 1 0x4f digit 0 annunciators 0 1 0 1 0 0 0 0 0x50 digit 1 annunciators 0 1 0 1 0 0 0 1 0x51 digit 2 annunciators 0 1 0 1 0 0 1 0 0x52 up to digit 45 annunciators 0 1 1 1 1 1 0 1 0x7d digit 46 annunciators 0 1 1 1 1 1 1 0 0x7e digit 47 annunciators 0 1 1 1 1 1 1 1 0x7f table 4. character and annunciator register address map in 48/1 mode
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller 12 ______________________________________________________________________________________ down mode is overridden when in display test mode. for normal operation, set s bit to 1. when the MAX6853 is in shutdown mode, the multiplex oscillator is halted at the end of the current 100s multi- plex period (osc = 4mhz), and the vfblank output is used to disable the vfd tube driver. data in the digit and other control registers remains unaltered. if the pump output is configured as a square-wave clock, then the pump output is forced low for the dura- tion of shutdown, and the square-wave clock restored when the MAX6853 comes out of shutdown. if the phase1 output or phase2 output is configured as a filament driver, then that output is forced low for the duration of shutdown and the filament drive waveforms restored when the MAX6853 comes out of shutdown. when the MAX6853 comes out of shutdown, the exter- nal vfd tube driver is presumed to contain invalid data. the vfblank output is used to disable the vfd tube driver for the first multiplex cycle after exiting shutdown, clearing any invalid data. the next multiplex cycle uses newly sent valid data. configuration lock (l data bit d1) format the configuration lock register is a safety feature to reduce the risk of the vfd configuration settings being inadvertently changed due to spurious writes if soft- ware fails. when set, the shift-limit register (0x0e), grids register (0x03), and output map data (0x06) can be read but cannot be written. the output map data point- er itself may be written in order to allow the output map data to be read back (table 19). blink rate selection (b data bit d2) format the b bit in the configuration register selects the blink rate of the cursor and annunciator segments. this is the speed that the segments blink on and off when blinking is selected for these segments. the frequency of the multiplex clock osc and the setting of the b bit (table 20) determine the blink rate. command address register d15 d14 d13 d12 d11 d10 d9 d8 hex code digit 0 5 x 7 matrix character, 1st row 0 0 1 0 0 0 0 0 0x20 digit 1 5 x 7 matrix character, 1st row 0 0 1 0 0 0 0 1 0x21 digit 2 5 x 7 matrix character, 1st row 0 0 1 0 0 0 1 0 0x22 up to digit 45 5 x 7 matrix character, 1st row 0 1 0 0 1 1 0 1 0x4d digit 46 5 x 7 matrix character, 1st row 0 1 0 0 1 1 1 0 0x4e digit 47 5 x 7 matrix character, 1st row 0 1 0 0 1 1 1 1 0x4f digit 0 5 x 7 matrix character, 2nd row 0 1 0 1 0 0 0 0 0x50 digit 1 5 x 7 matrix character, 2nd row 0 1 0 1 0 0 0 1 0x51 digit 2 5 x 7 matrix character, 2nd row 0 1 0 1 0 0 1 0 0x52 up to digit 45 5 x 7 matrix character, 2nd row 0 1 1 1 1 1 0 1 0x7d digit 46 5 x 7 matrix character, 2nd row 0 1 1 1 1 1 1 0 0x7e digit 47 5 x 7 matrix character, 2nd row 0 1 1 1 1 1 1 1 0x7f table 5. character register address map in 96/2 mode register data mode command address d7 d6 d5 d4 d3 d2 d1 d0 writing character data to use font map data with dp segment unlit 0x20 to 0x4f (48/1 mode) 0x20 to 0x7f (96/2 mode) 0 writing character data to use font map data with dp segment lit 0x20 to 0x4f (48/1 mode) 0x20 to 0x7f (96/2 mode) 1 bits d6 to d0 select font characters 0 to 127 table 6. character registers format
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller ______________________________________________________________________________________ 13 global blink timing synchronization (t data bit d4) format setting the t bit in multiple MAX6853s at the same time (or in quick succession) synchronizes the blink timing across all the devices (table 21). the display multiplex- ing sequence is also reset, which can give rise to a one-time display flicker when the register is written. global clear digit data (r data bit d5) format when the r bit (table 22) is set, the segment and annunciator data are cleared. display mode (m data bit d6) format the m bit (table 23) selects the display modes (table 1). the display modes trade the maximum allowable num- ber of digits (mode 96/2) against the availability of annunciator segments (mode 48/1). blink phase readback (p data bit d7) format when the configuration register is read, the p bit reflects the blink phase at that time (table 24). serial interface serial addressing the MAX6853 operates as a slave that sends and receives data through an i 2 c-compatible 2-wire inter- face. the interface uses a serial data line (sda) and a serial clock line (scl) to achieve bidirectional commu- nication between master(s) and slave(s). a master (typ- ically a microcontroller) initiates all data transfers to and from the MAX6853, and generates the scl clock that synchronizes the data transfer (figure 6). the MAX6853 sda line operates as both an input and an open-drain output. a pullup resistor, typically 4.7k ? , is required on the sda. the MAX6853 scl line oper- ates only as an input. a pullup resistor, typically 4.7k ? , is required on scl if there are multiple masters on the 2-wire interface, or if the master in a single-master sys- tem has an open-drain scl output. each transmission consists of a start condition (figure 7) sent by a master, followed by the MAX6853 7-bit slave address plus r/ w bit (figure 10), a register address byte, 1 or more data bytes, and finally a stop condition (figure 7). start and stop conditions both scl and sda remain high when the interface is not busy. a master signals the beginning of a transmis- sion with a start (s) condition by transitioning sda from high to low while scl is high. when the master has finished communicating with the slave, it issues a stop (p) condition by transitioning the sda from low to high while scl is high. the bus is then free for another transmission (figure 7). bit transfer one data bit is transferred during each clock pulse. the data on the sda line must remain stable while scl is high (figure 8). acknowledge the acknowledge bit is a clocked 9th bit that the recipi- ent uses to handshake receipt of each byte of data (figure 9). thus, each byte transferred effectively requires 9 bits. the master generates the 9th clock pulse, and the recipient pulls down sda during the acknowledge clock pulse, such that the sda line is sta- ble low during the high period of the clock pulse. when the master is transmitting to the MAX6853, the MAX6853 generates the acknowledge bit because the MAX6853 is the recipient. when the MAX6853 is trans- mitting to the master, the master generates the acknowledge bit because the master is the recipient. in this case, the master acknowledges all bytes received from the MAX6853 except for the last byte required, after which the master issues a stop condition to signi- fy end of transmission. slave address the MAX6853 has a 7-bit-long slave address (figure 10). the eighth bit following the 7-bit slave address is the r/ w bit. set it low for a write command and high for a read command. the first 5 bits (msbs) of the MAX6853 slave address are always 11101. slave address bits a1 and a0 are selected by the address input pins ad0. this input may be connected to gnd, v+, sda, or scl. the MAX6853 has four possible slave addresses (table 7) and therefore a maximum of four MAX6853 devices may share the same interface. message format for writing a write to the MAX6853 comprises the transmission of the MAX6853's slave address with the r/ w bit set to zero, followed by at least 1 byte of information. the first byte of information is the command byte, which deter- mines which register of the MAX6853 is to be written by the next byte, if received. if a stop condition is detect- ed after the command byte is received, then the MAX6853 takes no further action (figure 11) beyond storing the command byte. any bytes received after the command byte are data bytes. the first data byte goes into the internal register of the MAX6853 selected by the command byte (figure 12). if multiple data bytes are transmitted before a stop con- dition is detected, these bytes are generally stored in subsequent MAX6853 internal registers because the
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller 14 ______________________________________________________________________________________ stop condition start condition t buf t su , sto t hd , sta repeated start condition t su , sta t hd , dat t su , dat t low sda scl t high start condition t hd , sta t r t f figure 6. 2-wire serial interface timing details sda scl s start condition stop condition p figure 7. start and stop conditions data line stable, data valid change of data allowed sda scl figure 8. bit transfer start condition 1 scl sda by transmitter sda by receiver s 2 8 7 9 clock pulse for acknowledgment figure 9. acknowledge sda scl start msb 1 1 1 0 1 a1 a0 r/w lsb ack figure 10. slave address
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller _______________________________________________________________________________________ 15 command byte address generally autoincrements (table 8) (figure 13). message format for reading the MAX6853 is read using the MAX6853's internally stored command byte as address pointer, the same way the stored command byte is used as address pointer for a write. the pointer generally autoincre- ments after each data byte is read using the same rules as for a write (table 8). thus, a read is initiated by first configuring the MAX6853's command byte by perform- ing a write (figure 11). the master can now read n con- secutive bytes from the MAX6853, with the first data byte being read from the register addressed by the ini- tialized command byte (figure 13). when performing read-after-write verification, reset the command byte's address because the stored byte address generally is autoincremented after the write (table 8). operation with multiple masters if the MAX6853 is operated on a 2-wire interface with multiple masters, a master reading the MAX6853 should use a repeated start between the write, which sets the MAX6853's address pointer, and the read(s) that takes the data from the location(s). this is because it is possible for master 2 to take over the bus after master sa ap 0 slave address command byte acknowledge from MAX6853 r/w acknowledge from MAX6853 d15 d14 d13 d12 d11 d10 d9 d8 command byte is stored on receipt of stop condition aa ap 0 slave address command byte data byte acknowledge from MAX6853 r/w 1 byte autoincrement memory word address acknowledge from MAX6853 acknowledge from MAX6853 d15 d14 d13 d12 d11 d10 d9 d8 d1 d0 d3 d2 d5 d4 d7 d6 how control byte and data byte map into MAX6853's registers s figure 12. command and single data byte received s aaap 0 slave address command byte data byte acknowledge from MAX6853 r/w n bytes autoincrement memory word address acknowledge from MAX6853 acknowledge from MAX6853 d15 d14 d13 d12 d11 d10 d9 d8 d1 d0 d3 d2 d5 d4 d7 d6 how command byte and data byte map into MAX6853's registers figure 13. n data bytes received pin device address ad0 a6 a5 a4 a3 a2 a1 a0 gnd1110100 v+ 1110101 sda1110110 scl 1110111 table 7. MAX6853 address map figure 11. command byte received
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller 16 ______________________________________________________________________________________ 1 has set up the MAX6853's address pointer but before master 1 has read the data. if master 2 subsequently changes the MAX6853's address pointer, then master 1's delayed read may be from an unexpected location. command address autoincrementing address autoincrementing allows the MAX6853 to be configured with the shortest number of transmissions by minimizing the number of times the command byte needs to be sent. the command address or the font pointer address stored in the MAX6853 generally incre- ments after each data byte is written or read (table 8). vfd driver serial interface the vfd driver interface on the MAX6853 is a serial interface using three outputs, vfload, vfclk, and vfdout (figure 14) to drive industry-standard, shift- register, high-voltage grid/anode vfd tube drivers (figures 3 and 4). the speed of vfclk is 2mhz when osc is 4mhz. the maximum speed of vfclk is 4mhz when osc is 8mhz. this interface transfers display data from the MAX6853 to the vfd tube driver. the ser- ial interface bit stream output is programmable up to 122 bits, which are labeled dd0 dd121. the functions of the three interface outputs are as fol- lows: vfclk is the serial clock output, which shifts data on its falling edge from the MAX6853 s 122-bit output shift register to vfload. vfdout is the serial data output. the data changes on vfclk s falling edge, and is stable when it is sampled by the display driver on the rising edge of vfclk. vfload is the latch-load output. vfload is high to transfer data from the display tube driver s shift register to the display driver s output latch (transparent mode), and low to retain that data in the display driver s output latch. a fourth output, vfblank, provides gating control of the tube driver. vfblank can be configured to be either high or low using the vblank polarity register (table 27) to enable the vfd tube driver. in the default condition, vfblank is high to disable the vfd tube dri- ver, which is expected to force its driver outputs low to blank the display without altering the contents of its out- put latches. in the default condition, vfblank is low to enable its vfd tube driver outputs to follow the state of the vfd tube driver s output latches. the vfblank output is used for pwm intensity control and to disable the vfd tube driver in shutdown. multiplex architecture the multiplex engine transmits grid and anode control data to the external vfd driver using the vfclk, vfd- out, and vfload. the number of data bits m trans- mitted is set by the user in the shift-limit register (table 29). figure 15 is the vfd multiplex timing diagram. the essential rules for multiplex action are as follows: the external vfd driver s data latch contains the data for the current grid being displayed. the vfblank input is controlled to provide the pwm intensity control. the vfclk and vfdout outputs are used to fill the external vfd driver s shift register with the multiplex data for the next grid, during the multiplex timeslot for the current grid. the vfload output loads the new grid-anode data pattern at the start of its multiplex cycle. grids register the grids register sets how many grids are multiplexed from 1 to 48 (table 25). when the grids register is written, the external vfd tube driver is presumed to contain invalid data. the vfblank output disables the vfd tube driver for the first multiplex cycle after exiting shutdown, clearing any invalid data. the next multiplex cycle uses newly sent valid data. if the grids register is written with an out-of- range value of 0x30 to 0xff, then the value 0x2f is stored instead. command byte address range autoincrement behavior x0000000 to x0000100 command byte address autoincrements after byte read or written. x0000110 command byte address remains at x0000110 after byte read or written, but the font output map address pointer autoincrements. x0010000 factory reserved; do not write to this register. x000111 to x1111110 command byte address autoincrements after byte read or written. x1111111 command byte address remains at x1111111 after byte read or written. table 8. command address autoincrement rules
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller ______________________________________________________________________________________ 17 intensity register digital control of display brightness is provided by pulse-width modulation of the tube blanking time, which is controlled by the lower nibble of the intensity register (table 26). the modulator scales the vfblank output in 15 steps from a minimum of 1/16 up to 15/16 of each grid s multiplex period (figure 16). figure 17 shows the modulator behavior when the vfblank polarity regis- ter is set to 0x00 (table 27), so vfblank is high to dis- able (blank) the display. the minimum off-time period of a 1/16 multiplex period (6.25s with osc = 4mhz) is always at the start of the multiplex cycle. this allows time for slow display drivers to turn off, and slow display phosphors time to decay between grids. thus, image ghosting is avoided. if a display has very slow phosphor, double the allowed decay time by not using a 15/16 duty cycle. vfblank polarity register the vfblank polarity register sets the active level of the vfblank output pin (table 27). no-op register a write to the no-op register is ignored. display-test and device id register writing the display-test and device id register switches the drivers between one of two modes: normal and dis- play test. display-test mode turns all segments and annunciators on and sets the duty cycle to 7/16 (half- power) (table 28). reading the display-test and device id register returns the MAX6853 device id 0b0000 011 that identifies the driver type, plus the display-test status in the lsb. output shift-limit register the output serial interface transfers display data from the MAX6853 to the display driver. the serial interface bit-stream output length is programmable up to 122 bits, which are labeled dd0 dd121. set the number of bits with the shift-limit register, address 0x0e. if the shift-limit register is written with an out-of-range value 0x7a to 0xff, then the value 0x79 is stored instead. table 29 shows the shift-limit register. output map the output map comprises 122 words of 7-bit ram. the output map data should be written when the MAX6853 is configured after power-up. table 30 shows the output map ram codes. ram15 ram14 ram13 ram12 ram11 ram10 ram09 ram08 ram07 ram05 ram04 ram03 ram02 ram01 ram00 ram16 ram17 ram18 ram19 ram20 ram21 ram23 1111 1110 1101 1100 1011 1010 1001 1000 0111 ram06 ram22 0110 0101 0100 0011 0010 0001 0000 msb lsb x000 x001 x010 x011 x100 x101 x110 x111 table 9. character map
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller 18 ______________________________________________________________________________________ the output map is an indirect addressing reference table. it translates bit position in the output shift register (valid range: from zero to the value in shift-limit register 0x0e) to bit function. any output shift-register bit posi- tion may be set to any grid, 5 x 7 matrix segment, dp segment, annunciator segment, or cursor segment. the power-up default pattern for output map ram maps a 40-digit, two-digits-per-grid display with dps and cursors (table 31). selecting an unused map ram entry (126 or 127) for an output shift-register position always resets the corre- sponding output bit to low (segment or grid off). when selecting an invalid map ram entry (for example, codes 48 to 83 to select annunciators in 96/2 mode, which does not support annunciators), the correspond- ing output bit is always low (segment or grid off). if the map ram entry corresponds to a nonexistent font segment (no action in table 30) when the digit data is processed through the character font, then the result again is zero (segment or grid off). the output map data is indirectly accessed by an autoincrementing output map address pointer in the MAX6853 at address 0x06. the output map address pointer can be written (i.e., set to an address between 0x00 and 0x79) but cannot be read back. the output map data is written and read back through the output map address pointer. table 32 shows how to set the output map address pointer to a value within the acceptable range. bit d7 is set to denote that the user is writing the output map address pointer. if the user attempts to set the output map address to one of the out-of-range addresses by writing data in range 0xfa to 0xff, then address 0x00 is set instead. t vcl t vds t vch t vcp t vcsh t vcsw vfclk vfload m (m is value in shift-limit register) vfdout dd0 dd1 m-1 figure 14. vfd interface timing diagram vfclk vfdout vfload dd0 dd1 dd2 dd3 dd4 dd5 dd6 dd7 dd8 dd9 dd10 m-4 m-3 m-2 m-1 m (m is value in shift-limit register) grid 1's data, sent during grid 0's timeslot grid 0's 100 s multiplex timeslot one complete multiplex cycle around n grids (osc = 4mhz) start of next cycle 500ns 500ns 500ns 500ns 100 s timeslot grid 0 100 s timeslot grid 1 100 s timeslot grid n-4 100 s timeslot grid n-3 100 s timeslot grid n-2 100 s timeslot grid n-1 100 s timeslot grid 0 figure 15. vfd multiplex timing diagram
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller ______________________________________________________________________________________ 19 grid 0's 100 s multiplex timeslot one complete multiplex cycle around n grids (osc = 4mhz) start of next cycle 100 s timeslot grid 0 100 s timeslot grid 1 100 s timeslot grid n-4 100 s timeslot grid n-3 100 s timeslot grid n-2 100 s timeslot grid n-1 100 s timeslot grid 0 minimum 6.25 s interdigit blanking interval (osc = 4mhz) vfblank 1/16th (min on) 2/16th 3/16th 4/16th 5/16th 6/16th 7/16th 8/16th 9/16th 10/16th 11/16th 12/16th 13/16th 14/16th 15/16th 15/16th (max on) figure 16. blank and intensity timing diagram
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller 20 ______________________________________________________________________________________ after the last data location 0xf9 has been written, fur- ther output map data entries are ignored until the out- put map address pointer is reset. the output map data can be written to the address set by the output map address pointer. bit d7 is clear to denote that the user is writing actual output map data. the output map address pointer is autoincremented after the output map data has been written to the cur- rent location. if the user writes the output map data in the ram order, then the output map address pointer need only be set once, or even not at all as the address is set to 0x00 as power-up default (table 33). the output map data can be read by reading address 0x86. the 7-bit output map data at the address set by the output map address pointer is read back, with the msb clear. the output map address pointer is autoin- cremented after the output map data has been read from the current location, in the same way as for a write (table 34). filament drive the vfd filament is typically driven with an ac wave- form, supplied by a center-tapped 50hz or 60hz power transformer as part of the system power supply. however, if the system has only dc supplies available, the filament must be powered by a dc-to-ac or dc-to- dc converter. the MAX6853 can generate the waveforms on the phase1 and phase2 outputs to drive the vfd filament using a full bridge (push-pull drive). the phase1 and phase2 outputs can be used as general-purpose out- puts if the filament drive is not required. the bridge drive transistors are external, but the waveforms are generated by the MAX6853. the waveform generation uses pwm to set the effective rms voltage across the filament, as a fraction of the external supply voltage (figure 18) (table 35). the fila- ment switching frequency is synchronized to the multi- plex scan clock, eliminating beating artifacts due to differing filament and multiplex frequencies. the pwm duty cycle is controlled by the filament duty- cycle register (table 36). the effective rms voltage across the filament is given by the expression: v rms = filon x (v fil - v lo-bridge - v hi-bridge ) / 200 or, rearranged: duty = 200 x v rms / (v fil - v lo-bridge - v hi-bridge ) where: 2-1 seg 2 3-1 seg 3 4-1 seg 4 5-1 seg 5 1-2 seg 6 2-2 seg 7 3-2 seg 8 4-2 seg 9 5-2 seg 10 1-3 seg 11 2-3 seg 12 3-3 seg 13 4-3 seg 14 5-3 seg 15 1-4 seg 16 2-4 seg 17 3-4 seg 18 4-4 seg 19 5-4 seg 20 1-5 seg 21 2-5 seg 22 3-5 seg 23 4-5 seg 24 5-5 seg 25 1-6 seg 26 2-6 seg 27 3-6 seg 28 4-6 seg 29 5-6 seg 30 1-7 seg 31 2-7 seg 32 3-7 seg 33 4-7 seg 34 5-7 seg 35 1-1 seg 1 cursor figure 17. relationship between segment output and vfd tube 5 ? 7 matrix dots (a) (b) (c) (d) (e) 100 s multiplex time period (osc = 4mhz) phase 1 phase 2 figure 18. filament bridge driver timing waveforms r2 r4 q2 q1 gnd q3 q4 phase 1 phase 2 vfil vfd tube gnd figure 19. filament bridge driver (mosfet)
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller ______________________________________________________________________________________ 21 filon is the number to store in the filament duty-cycle register, address 0x09. v fil is the supply voltage to the filament driver bridge (v). v rms is the specified nominal filament supply voltage (v). v lo-bridge is the voltage drop across a low-side bridge driver (v). v hi-bridge is the voltage drop across a high-side bridge driver (v). the minimum commutation time, shown at (c) in figure 18, is set by (2/osc)s (500ns when osc = 4mhz) to ensure that shoot-through currents cannot flow during phase reversal. otherwise, the duty cycle of the bridge sets the rms voltage across the filament. this tech- nique provides a low-cost ac filament supply when using a regulated supply higher than the rms voltage rating of the filament. figure 19 shows the external components required for the filament driver using a fet bridge. phase1 and phase2 outputs phase1 and phase2 can be individually programmed as one of four output types (tables 37, 38). when using the filament drive, first ensure that the fila- ment duty-cycle register 0x09 is set to the correct value before configuring the phase1 and phase2 outputs to be filament drives. to stop the filament drive, program either phase1 or phase2 (or both) to be logic-low gen- eral-purpose outputs. both phase1 and phase2 out- puts come out of power-on-reset in logic-low condition. port0 and port1 outputs port0 and port1 can be individually programmed as one of eight output types (tables 39, 40). the port1 choices are similar to the port0 choices, except that the last four items are invert logic. port0 output comes out of power-on-reset in logic-low condition, whereas port1 output initializes high. the port0 and port1 shutdown outputs allow exter- nal hardware (for example, a dc-to-dc converter power supply for vfd) to be disabled by the MAX6853 when the MAX6853 is shut down. the 625hz, 1250hz, and 2500hz outputs can drive a piezo sounder either from port0 or port1 alone, or by both ports together as bridge drive. for bridge drive, the sounder is connected between port0 and port1, taking advantage of the port1 output being inverted with respect to port0. select different fre- quencies for port0 and port1 to obtain a wider range of sounds when bridge drive is used. pump output program the pump output as one of four output types (table 41). multiplex clock and blink timing the osc1 and osc2 inputs set the multiplex and blink timing for the display driver. connect an external resis- tor from osc2 to gnd and an external capacitor c osc from osc1 to gnd to set the frequency of the internal rc oscillator. alternatively, overdrive osc1 with an external ttl or cmos clock. use an external clock ranging between 2mhz and 8mhz to drive osc1 to produce an exact blink rate or multiplier period. the multiplex clock frequency determines the multiplex scan rate and the blink timing. the display scan rate is {osc / 400 / (1 + grids register value)}. there are 400 osc cycles per digit multiplex period. for example, with osc = 4mhz, each display digit is enabled for 100s. for a 40-grid display tube (grids register value = 39 or 0x27), the display scan rate is 250hz. the blink output is the selectable blink period clock. it is nominally 0.5hz or 1hz (osc = 4mhz). it is low dur- ing the first half of the blink period, and high during the second half. the port0 and port1 general-purpose outputs may be programmed to be blink output. synchronize the blink timing if desired by setting the t bit in the configuration register (table 21). the rc oscillator uses an external resistor r osc and an external capacitor c osc to set the oscillator fre- quency. r osc connects from osc2 to ground. c osc connects from osc1 to ground. the following values of r osc and c osc set the oscillator to 4mhz, which makes the blink frequencies 0.5hz and 1 hz: f osc = k f / (r osc x [c osc + c stray ]) mhz where: k f = 2320 r osc = external resistor in k ? (allowable range 8k ? to 80k ? ) c osc = external capacitor in pf c stray = stray capacitance from osc1 to gnd in pf, typically 2pf for osc = 4mhz, r osc is 10k ? and c osc is 56pf. the effective value of c osc includes not only the actual external capacitor used, but also the stray capacitance from osc1 to gnd. this capacitance is usually in the 1pf to 5pf range, depending on the layout used. the allowed range of f osc is 2mhz to 8mhz. if f osc is set too high, the internal oscillator can stop working. an internal fail-safe circuit monitors the multiplex clock and
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller 22 ______________________________________________________________________________________ detects a slow or nonworking multiplex clock. when a slow or nonworking multiplex clock is detected, an internal fail-safe oscillator generates a replacement clock of about 200khz. this backup clock ensures that the vfd is not damaged by the multiplex operation halt- ing inadvertently. the scan rate for 16 digits is about 15hz in fail-safe mode, and the display flickers. a flick- ering display is a good indication that there is a prob- lem with the multiplex clock. power supplies the MAX6853 operates from a single 2.7v to 3.6v power supply. bypass the power supply to gnd with a 0.1f capacitor as close to the device as possible. add a bulk capacitor (such as a low-cost electrolytic 1f to 22f) if the MAX6853 is driving high current from any of the general-purpose output ports. command address register data read or write function 0x05 0x00 0x7f read read 7-bit user-definable font data entry from current font address. msb of the register data is clear. font address pointer is incremented after the read. 0x05 0x00 0x7f write write 7-bit user-definable font data entry to current font address. font address pointer is incremented after the write. 0x05 0x80 0xff write write font address pointer with the register data. table 10. memory mapping of user-defined font register 0x05 font pointer address action 0x80 to 0xf6 valid range to set the font address pointer. pointer autoincrements after a font data read or write, while pointer address remains in this range. 0xf7 further font data is ignored after a font data read or write to this pointer address. 0xf8 to 0xff invalid range to set the font address pointer. pointer is set to 0x80. table 11. font pointer address behavior
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller ______________________________________________________________________________________ 23 register data font character command address register data d7 d6 d5 d4 d3 d2 d1 d0 ram00 0x05 0x80 10000000 ram01 0x05 0x85 10000101 ram02 0x05 0x8a 10001010 ram03 0x05 0x8f 10001111 ram04 0x05 0x94 10010100 ram05 0x05 0x99 10011001 ram06 0x05 0x9e 10011110 ram07 0x05 0xa3 10100011 ram08 0x05 0xa8 10101000 ram09 0x05 0xad 10101101 ram10 0x05 0xb2 10110010 ram11 0x05 0xb7 10110111 ram12 0x05 0xbc 10111100 ram13 0x05 0xc1 11000001 ram14 0x05 0xc6 11000110 ram15 0x05 0xcb 11001011 ram16 0x05 0xd0 11010000 ram17 0x05 0xd5 11010101 ram18 0x05 0xda 11011010 ram19 0x05 0xdf 11011111 ram20 0x05 0xe4 11100100 ram21 0x05 0xe9 11101001 ram22 0x05 0xee 11101110 ram23 0x05 0xf3 11110011 table 12. user-definable font pointer base address table
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller 24 ______________________________________________________________________________________ register data font character font address pointer command address d7 d6 d5 d4 d3 d2 d1 d0 ram00 0x00 0x05 0 0 1 1 1 1 1 0 ram00 0x01 0x05 0 1 0 1 000 1 ram00 0x02 0x05 0 1 00 1 00 1 ram00 0x03 0x05 0 1 000 1 0 1 ram00 0x04 0x05 0 0 1 1 1 1 1 0 ram01 0x05 0x05 00000000 ram01 0x06 0x05 0 1 0000 1 0 ram01 0x07 0x05 0 1 1 1 1 1 1 1 ram01 0x08 0x05 0 1 000000 ram01 0x09 0x05 00000000 ram02 0x0a 0x05 0 1 0000 1 0 ram02 0x0b 0x05 0 1 1 0000 1 ram02 0x0c 0x05 0 1 0 1 000 1 ram02 0x0d 0x05 0 1 00 1 00 1 ram02 0x0e 0x05 0 1 000 1 1 0 table 13. user-definable character storage example command address register data action being performed 0x05 0x8a set font address pointer to the base address of font character ram02. 0x05 0x42 1st 7 bits of data: 1000010 goes to font address 0x8a; pointer then autoincrements to address 0x8b. 0x05 0x61 2nd 7 bits of data: 1100001 goes to font address 0x8b; pointer then autoincrements to address 0x8c. 0x05 0x51 3rd 7 bits of data: 1010001 goes to font address 0x8c; pointer then autoincrements to address 0x8d. 0x05 0x49 4th 7 bits of data: 1001001 goes to font address 0x8d; pointer then autoincrements to address 0x8e. 0x05 0x46 5th 7 bits of data: 1000110 goes to font address 0x8e; pointer then autoincrements to address 0x8f. table 14. setting a font character to ram example register data mode command address d7 d6 d5 d4 d3 d2 d1 d0 cursor register. 0x0f blink cursor position digit 1's cursor is lit continuously. 0x0f 0 0 0 0 0 0 0 0 digit 1's cursor is lit only for the first half of each blink period. 0x0f 1 0 0 0 0 0 0 0 up to 0x0f up to digit 96's cursor is lit continuously. 0x0f 0 1 0 1 1 1 1 1 digit 96's cursor is lit only for the first half of each blink period. 0x0f 1 1 0 1 1 1 1 1 no cursor is lit. 0x0f x 1 1 x x x x x table 15. cursor register format
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller ______________________________________________________________________________________ 25 register data annunciator byte d7 d6 d5 d4 d3 d2 d1 d0 bit allocations annunciator a4 annunciator a3 annunciator a2 annunciator a1 annunciator a1 is off. xxxxxx00 annunciator a1 is lit only for the first half of each blink period. xxxxxx01 annunciator a1 is lit only for the second half of each blink period. xxxxxx10 annunciator a1 is lit continuously. xxxxxx11 annunciator a2 is off. xxxx00xx annunciator a2 is lit only for the first half of each blink period. xxxx01xx annunciator a2 is lit only for the second half of each blink period. xxxx10xx annunciator a2 is lit continuously. xxxx11xx annunciator a3 is off. x x 0 0 x x x x annunciator a3 is lit only for the first half of each blink period. xx01xxxx annunciator a3 is lit only for the second half of each blink period. xx10xxxx annunciator a3 is lit continuously. x x 1 1 x x x x annunciator a4 is off. 0 0 x x x x x x annunciator a4 is lit only for the first half of each blink period. 01xxxxxx annunciator a4 is lit only for the second half of each blink period. 10xxxxxx annunciator a4 is lit continuously. 1 1 x x x x x x table 16. annunciator registers format register data mode d7 d6 d5 d4 d3 d2 d1 d0 configuration register pmr t xb l s table 17. configuration register format register data mode d7 d6 d5 d4 d3 d2 d1 d0 shutdown p m r t x b l 0 normal operation p m r t x b l 1 table 18. shutdown control (s data bit d0) format register data mode d7 d6 d5 d4 d3 d2 d1 d0 unlocked p m r t x b 0 s locked p m r t x b 1 s table 19. configuration lock (l data bit d1) format
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller 26 ______________________________________________________________________________________ register data mode d7 d6 d5 d4 d3 d2 d1 d0 slow blinking (cursor and annunciators blink on for 1s, off for 1s, for osc = 4mhz) p m r t x 0 l s fast blinking (cursor and annunciators blink on for 0.5s, off for 0.5s, for osc = 4mhz) p m r t x 1 l s table 20. blink rate selection (b data bit d2) format register data mode d7 d6 d5 d4 d3 d2 d1 d0 blink timing counters are unaffected. p m r 0 x b l s blink timing counters are cleared during the i 2 c acknowledge. p m r 1 x b l s table 21. global blink timing synchronization (t data bit d4) format register data mode d7 d6 d5 d4 d3 d2 d1 d0 segment and annunciator data are unaffected. p m 0 t x b l s segment and annunciator data (address range 0x20 to 0x7f) are cleared during the i 2 c acknowledge. pm1 txbl s table 22. global clear digit data (r data bit d5) format register data mode display type d7 d6 d5 d4 d3 d2 d1 d0 48/1 up to 48 digits, 1 digit per grid p 0 r t x b l s 96/2 up to 96 digits, 2 digits per grid p 1 r t x b l s table 23. display mode (m data bit d6) format register data mode d7 d6 d5 d4 d3 d2 d1 d0 p1 blink phase 0 m r t x b l s p0 blink phase 1 m r t x b l s table 24. blink phase readback (p data bit d7) format
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller ______________________________________________________________________________________ 27 register data grids command address d7 d6 d5 d4 d3 d2 d1 d0 hex code display has 1 grid: g0 0x03 0 0 0 0 0 0 0 0 0x00 display has 2 grids: g0 and g1 0x03 0 0 0 0 0 0 0 1 0x01 display has 3 grids: g0 to g2 0x03 0 0 0 0 0 0 1 0 0x02 display has 4 grids: g0 to g3 0x03 0 0 0 0 0 0 1 1 0x03 up to 0x03 0 0 display has 45 grids: g0 to g44 0x03 0 0 1 0 1 1 0 0 0x2c display has 46 grids: g0 to g45 0x03 0 0 1 0 1 1 0 1 0x2d display has 47 grids: g0 to g46 0x03 0 0 1 0 1 1 1 0 0x2e display has 48 grids: g0 to g47 0x03 0 0 1 0 1 1 1 1 0x2f table 25. grids register format register data duty cycle vfblank behavior (osc = 4mhz) command address d7 d6 d5 d4 d3 d2 d1 d0 hex code 1/16 (min on) high for 6.25s, low for 6.25s, high for 87.5s 0x02 xxxx 0000 0xx0 2/16 high for 6.25s, low for 12.5s, high for 81.25s 0x02 xxxx 0001 0xx1 3/16 high for 6.25s, low for 18.75s, high for 75s 0x02 xxxx 0010 0xx2 4/16 high for 6.25s, low for 25s, high for 68.75s 0x02 xxxx 0011 0xx3 5/16 high for 6.25s, low for 31.25s, high for 62.5s 0x02 xxxx 0100 0xx4 6/16 high for 6.25s, low for 37.5s, high for 56.25s 0x02 xxxx 0101 0xx5 7/16 high for 6.25s, low for 43.75s, high for 50s 0x02 xxxx 0110 0xx6 8/16 high for 6.25s, low for 50s, high for 43.75s 0x02 xxxx 0111 0xx7 9/16 high for 6.25s, low for 56.25s, high for 37.5s 0x02 xxxx 1000 0xx8 10/16 high for 6.25s, low for 62.5s, high for 31.25s 0x02 xxxx 1001 0xx9 11/16 high for 6.25s, low for 68.75s, high for 25s 0x02 xxxx 1010 0xxa 12/16 high for 6.25s, low for 75s, high for 18.75s 0x02 xxxx 1011 0xxb 13/16 high for 6.25s, low for 81.25s, high for 12.5s 0x02 xxxx 1100 0xxc 14/16 high for 6.25s, low for 87.5s, high for 6.25s 0x02 xxxx 1101 0xxd 15/16 high for 6.25s, low for 93.75s 0x02 xxxx 1110 0xxe 15/16 (max on) high for 6.25s, low for 93.75s 0x02 xxxx 1111 0xxf table 26. intensity register format
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller 28 ______________________________________________________________________________________ register data grids command address d7 d6 d5 d4 d3 d2 d1 d0 hex code vfblank is high to disable the display. 0x01 x x x x x x 0 0 0xx0 vfblank is low to disable the display. 0x01 x x x x x x 1 0 0xx2 table 27. vfblank polarity register format register data mode command address d7 d6 d5 d4 d3 d2 d1 d0 normal operation 0x07 xxxxxxx0 display test 0x07 xxxxxxx1 read MAX6853 device id and display test status 0x07 0000011dt table 28. display-test and device id register format register data shift limit command address d7 d6 d5 d4 d3 d2 d1 d0 hex code minimum setting example (01) 0x0e 0 0 0 0 0 0 0 1 0x01 maximum setting example (121 or 0x79) 0x0e 0 1 1 1 1 0 0 1 0x79 table 29. shift-limit register format
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller ______________________________________________________________________________________ 29 output map ram code (decimal) application function mapped by output map ram code 0 to 47 48 grids grids g0 to g47 48, 49, 50, 51, 52 5 x 7 matrix character segments 1-1, 2-1, 3-1, 4-1, 5-1 53, 54, 55, 56, 57 5 x 7 matrix character segments 1-2, 2-2, 3-2, 4-2, 5-2 58, 59, 60, 61, 62 5 x 7 matrix character segments 1-3, 2-3, 3-3, 4-3, 5-3 63, 64, 65, 66, 67 5 x 7 matrix character segments 1-4, 2-4, 3-4, 4-4, 5-4 68, 69, 70, 71, 72 5 x 7 matrix character segments 1-5, 2-5, 3-5, 4-5, 5-5 73, 74, 75, 76, 77 5 x 7 matrix character segments 1-6, 2-6, 3-6, 4-6, 5-6 78, 79, 80, 81, 82 5 x 7 matrix character segments 1-7, 2-7, 3-7, 4-7, 5-7 83 5 x 7 matrix character segments digits 0 to 47 only use character registers 0x20 to 0x4f (figure 12) 5 x 7 matrix character segment dp 84, 85, 86, 87, 88 5 x 7 matrix character segments digits 48 to 95 only use character registers 0x50 to 0x7f (figure 12) only valid for 96/2 mode (display mode select bit m = 1) 5 x 7 matrix character segments 1-1, 2-1, 3-1, 4-1, 5-1 89, 90, 91, 92, 93 5 x 7 matrix character segments 1-2, 2-2, 3-2, 4-2, 5-2 94, 95, 96, 97, 98 5 x 7 matrix character segments 1-3, 2-3, 3-3, 4-3, 5-3 99, 100, 101,102, 103 5 x 7 matrix character segments 1-4, 2-4, 3-4, 4-4, 5-4 104, 105, 106, 107, 108 5 x 7 matrix character segments 1-5, 2-5, 3-5, 4-5, 5-5 109, 110, 111, 112, 113 5 x 7 matrix character segments 1-6, 2-6, 3-6, 4-6, 5-6 114, 115, 116, 117, 118 5 x 7 matrix character segments 1-7, 2-7, 3-7, 4-7, 5-7 119 5 x 7 matrix character segment dp 120 to 123 4 annunciators only valid for 48/1 mode (display mode select bit m = 0) annunciator a1 to annunciator a4 124 cursor cursor segment for digits 0 to 47 only 125 cursor only valid for 96/2 mode (display mode select bit m = 1) cursor segment for digits 48 to 95 only 126, 127 unused no action table 30. output map ram codes
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller 30 ______________________________________________________________________________________ output map ram address output map ram code on power-up (decimal) function mapped by output map ram code 0x00 to 0x27 0 39 grids 0 39 0x28, 0x29, 0x2a, 0x2b, 0x2c 48, 49, 50, 51, 52 5 x 7 matrix character segments 1-1, 2-1, 3-1, 4-1, 5-1 0x2d, 0x2e, 0x2f, 0x30, 0x31 53, 54, 55, 56, 57 5 x 7 matrix character segments 1-2, 2-2, 3-2, 4-2, 5-2 0x32, 0x33, 0x34, 0x35, 0x36 58, 59, 60, 61, 62 5 x 7 matrix character segments 1-3, 2-3, 3-3, 4-3, 5-3 0x37, 0x38, 0x39, 0x3a, 0x3b 63, 64, 65, 66, 67 5 x 7 matrix character segments 1-4, 2-4, 3-4, 4-4, 5-4 0x3c, 0x3d, 0x3e, 0x3f, 0x40 68, 69, 70, 71, 72 5 x 7 matrix character segments 1-5, 2-5, 3-5, 4-5, 5-5 0x41, 0x42, 0x43, 0x44, 0x45 73, 74, 75, 76, 77 5 x 7 matrix character segments 1-6, 2-6, 3-6, 4-6, 5-6 0x46, 0x47, 0x48, 0x49, 0x4a 78, 79, 80, 81, 82 5 x 7 matrix character segments 1-7, 2-7, 3-7, 4-7, 5-7 0x4b 83 5 x 7 matrix character segment dp 0x4c, 0x4d, 0x4e, 0x4f, 0x50 84, 85, 86, 87, 88 5 x 7 matrix character segments 1-1, 2-1, 3-1, 4-1, 5-1 0x51, 0x52, 0x53, 0x54, 0x55 89, 90, 91, 92, 93 5 x 7 matrix character segments 1-2, 2-2, 3-2, 4-2, 5-2 0x56, 0x57, 0x58, 0x59, 0x5a 94, 95, 96, 97, 98 5 x 7 matrix character segments 1-3, 2-3, 3-3, 4-3, 5-3 0x5b, 0x5c, 0x5d, 0x5e, 0x5f 99, 100, 101,102, 103 5 x 7 matrix character segments 1-4, 2-4, 3-4, 4-4, 5-4 0x60, 0x61, 0x62, 0x63, 0x64 104, 105, 106, 107, 108 5 x 7 matrix character segments 1-5, 2-5, 3-5, 4-5, 5-5 0x65, 0x66, 0x67, 0x68, 0x69 109, 110, 111, 112, 113 5 x 7 matrix character segments 1-6, 2-6, 3-6, 4-6, 5-6 0x6a, 0x6b, 0x6c, 0x6d, 0x6e 114, 115, 116, 117, 118 5 x 7 matrix character segments 1-7, 2-7, 3-7, 4-7, 5-7 0x6f 119 5 x 7 matrix character segment dp 0x70 124 cursor segment for digits 0 to 47, 1st row 0x71 125 cursor segment for digits 0 to 47, 2nd row 0x72 to 0x79 127 no action table 31. output map ram initial power-up status register data mode command address d7 d6 d5 d4 d3 d2 d1 d0 set output map address to minimum (0x00) with data 0x80. (note that this address is set as a power-up default.) 0x06 1 0 0 0 0 0 0 0 set output map address to maximum 0x79 with data 0xf9. 0x06 1 1 1 1 1 0 0 1 table 32. setting output map address pointer register data mode command address d7 d6 d5 d4 d3 d2 d1 d0 write output map data; output map address pointer is autoincremented after the output map data has been written to the current location. 0x06 0 7 bits of output map data table 33. writing output map data
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller ______________________________________________________________________________________ 31 register data mode command address d7 d6 d5 d4 d3 d2 d1 d0 read output map data; output map address pointer is autoincremented after the output map data has been read from the current location. 0x06 0 7 bits of output map data table 34. reading output map data register data filament duty cycle command address d7 d6 d5 d4 d3 d2 d1 d0 hex code minimum setting example (01) 0x09 0 0 0 0 0 0 0 1 0x01 maximum setting example (199 or 0xc7) 0x09 1 1 0 0 0 1 1 1 0xc7 table 36. filament duty-cycle register format register data phase1 behavior command address d7 d6 d5 d4 d3 d2 d1 d0 hex code general-purpose output, logic 0. this is the power-up condition. 0x0a x x x x x x 0 0 0xx0 general-purpose output, logic 1. 0x0a x x x x x x 0 1 0xx1 output gives blink status: zero if blink phase p0; 1 if blink phase p1. 0x0a x x x x x x 1 0 0xx2 filament drive phase1 (logic 0 during shutdown). 0x0a x x x x x x 1 1 0xx3 table 37. phase1 register format timing point phase1 behavior phase2 behavior example 1 duty = 1 (min) example 2 duty = 100 example 3 duty = 198 (a) low for (199 - filon) cycles low for (199 - filon) cycles 198 99 1 (b) low for (filon) cycles high for (filon) cycles 1 100 198 (c) low for (2) cycles low for (2) cycles 2 2 2 (d) high for (filon) cycles low for (filon) cycles 1 100 198 (e) low for (199 - filon) cycles low for (199 - filon) cycles 198 99 1 total 4mhz cycles (osc = 4mhz) 400 cycles = 100s 400 cycles = 100s 400 cycles = 100s 400 cycles = 100s 400 cycles = 100s table 35. filament bridge driver timing
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller 32 ______________________________________________________________________________________ register data phase2 behavior command address d7 d6 d5 d4 d3 d2 d1 d0 hex code general-purpose output, logic 0. this is the power-up condition. 0x0b x x x x x x 0 0 0xx0 general-purpose output, logic 1. 0x0b x x x x x x 0 1 0xx1 output gives blink status: zero if blink phase p0; 1 if blink phase p1. 0x0b x x x x x x 1 0 0xx2 filament drive phase2 (logic 0 during shutdown). 0x0b x x x x x x 1 1 0xx3 table 38. phase2 register format register data port0 port behavior command address d7 d6 d5 d4 d3 d2 d1 d0 hex code general-purpose output, logic 0. this is the power-up condition. 0x0c x x x x x 0 0 0 0xx0 general-purpose output, logic 1. 0x0c x x x x x 0 0 1 0xx1 outp ut g i ves b l i nk status: zer o i f b l i nk p hase p 0; 1 if blink phase p1. 0x0c x x x x x 0 1 0 0xx2 output blink status: 1 if blink phase p0; zero if blink phase p1. 0x0c x x x x x 0 1 1 0xx3 625hz square-wave output zero in shutdown. 0x0c x x x x x 1 0 0 0xx4 1250hz square-wave output zero in shutdown. 0x0c x x x x x 1 0 1 0xx5 2500hz square-wave output zero in shutdown. 0x0c x x x x x 1 1 0 0xx6 output gives shutdown status: zero if shutdown mode; 1 if operating mode. 0x0c x x x x x 1 1 1 0xx7 table 39. port0 register format
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller ______________________________________________________________________________________ 33 register data port1 port behavior command address d7 d6 d5 d4 d3 d2 d1 d0 hex code general-purpose output, logic 0. 0x0d x x x x x 0 0 0 0xx0 general-purpose output, logic 1. this is the power-up condition. 0x0d x x x x x 0 0 1 0xx1 output gives blink status: zero if blink phase p0; 1 if blink phase p1. 0x0d x x x x x 0 1 0 0xx2 output blink status: 1 if blink phase p0; zero if blink phase p1. 0x0d x x x x x 0 1 1 0xx3 inverted 625hz square-wave output 1 in shutdown. 0x0d x x x x x 1 0 0 0xx4 inverted 1250hz square-wave output 1 in shutdown. 0x0d x x x x x 1 0 1 0xx5 inverted 2500hz square-wave output 1 in shutdown. 0x0d x x x x x 1 1 0 0xx6 output gives inverted shutdown status: 1 if shutdown mode; zero if operating mode. 0x0d x x x x x 1 1 1 0xx7 table 40. port1 register format register data pump port behavior command address d7 d6 d5 d4 d3 d2 d1 d0 hex code general-purpose output, logic 0. this is the power-up condition. 0x08 x x x x x x 0 0 0xx0 general-purpose output, logic 1. 0x08 x x x x x x 0 1 0xx1 80khz square-wave output (osc = 4mhz) (logic 0 during shutdown). 0x08 x x x x x x 1 0 0xx2 80khz square-wave output (osc = 4mhz) (logic 1 during shutdown). 0x08 x x x x x x 1 1 0xx3 table 41. pump register format
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller 34 ______________________________________________________________________________________ osc1 osc2 vfblank scl sda ad0 2-wire serial interface ram configuration registers character- generator rom output map ram user outputs filament pwm clock generator pwm brightness control vfclk vfdout vfload phase 2 phase 1 pump port 0 port 1 output shifter MAX6853 functional diagram 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 vfclk osc1 osc2 port1 sda scl port0 gnd top view MAX6853 vfdout vfload phase1 vfblank pump phase2 v+ ad0 qsop pin configuration chip information transistor count: 199,083 process: cmos
MAX6853 2-wire interfaced, 5 ? 7 matrix vacuum- fluorescent display controller maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 35 ? 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qsop.eps

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